CVE-2026-53374 (GCVE-0-2026-53374)
Vulnerability from cvelistv5
Published
2026-07-19 10:01
Modified
2026-08-05 12:35
Severity ?
8.8 (High) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
Summary
In the Linux kernel, the following vulnerability has been resolved: drm/amdgpu: zero-initialize GART table on allocation GART TLB is flushed after unmapping but not after mapping. Since amdgpu_bo_create_kernel() does not zero-initialize the buffer, when a single PTE is written the TLB may speculatively load other uninitialized entries from the same cacheline. Those garbage entries can appear valid, and a subsequent write to another PTE in the same cacheline may cause the GPU to use a stale garbage PTE from the TLB. Fix this by calling memset_io() to zero-initialize the GART table with gart_pte_flags immediately after allocation. Using AMDGPU_GEM_CREATE_VRAM_CLEARED, SDMA-based clear will not work since SDMA needs GART to be initialized to work. (cherry picked from commit d9af8263b82b6eaa60c5718e0c6631c5037e4b24)
References
Impacted products
Vendor Product Version
Linux Linux Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
Version: d38ceaf99ed015f2a0b9af3499791bd3a3daae21
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{
  "containers": {
    "cna": {
      "affected": [
        {
          "defaultStatus": "unaffected",
          "product": "Linux",
          "programFiles": [
            "drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c"
          ],
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          "programFiles": [
            "drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c"
          ],
          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
          "vendor": "Linux",
          "versions": [
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              "status": "unaffected",
              "version": "0",
              "versionType": "semver"
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              "status": "unaffected",
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              "version": "6.6.140",
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            },
            {
              "lessThanOrEqual": "6.18.*",
              "status": "unaffected",
              "version": "6.18.32",
              "versionType": "semver"
            },
            {
              "lessThanOrEqual": "7.0.*",
              "status": "unaffected",
              "version": "7.0.9",
              "versionType": "semver"
            },
            {
              "lessThanOrEqual": "*",
              "status": "unaffected",
              "version": "7.1",
              "versionType": "original_commit_for_fix"
            }
          ]
        }
      ],
      "cpeApplicability": [
        {
          "nodes": [
            {
              "cpeMatch": [
                {
                  "criteria": "cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*",
                  "versionEndExcluding": "6.1.175",
                  "versionStartIncluding": "4.2",
                  "vulnerable": true
                },
                {
                  "criteria": "cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*",
                  "versionEndExcluding": "6.6.140",
                  "versionStartIncluding": "4.2",
                  "vulnerable": true
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              ],
              "negate": false,
              "operator": "OR"
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          ]
        }
      ],
      "descriptions": [
        {
          "lang": "en",
          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\ndrm/amdgpu: zero-initialize GART table on allocation\n\nGART TLB is flushed after unmapping but not after mapping. Since\namdgpu_bo_create_kernel() does not zero-initialize the buffer, when a\nsingle PTE is written the TLB may speculatively load other uninitialized\nentries from the same cacheline. Those garbage entries can appear valid,\nand a subsequent write to another PTE in the same cacheline may cause the\nGPU to use a stale garbage PTE from the TLB.\n\nFix this by calling memset_io() to zero-initialize the GART table with\ngart_pte_flags immediately after allocation.\n\nUsing AMDGPU_GEM_CREATE_VRAM_CLEARED, SDMA-based clear will not work\nsince SDMA needs GART to be initialized to work.\n\n(cherry picked from commit d9af8263b82b6eaa60c5718e0c6631c5037e4b24)"
        }
      ],
      "metrics": [
        {
          "cvssV3_1": {
            "baseScore": 8.8,
            "baseSeverity": "HIGH",
            "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H",
            "version": "3.1"
          },
          "scenarios": [
            {
              "lang": "en",
              "value": "AV:L - The bug is reached when a local process with access to /dev/dri/renderD* issues AMDGPU DRM ioctls (GEM_CREATE, CS) that bind GTT buffers through amdgpu_ttm_backend_bind() \u2192 amdgpu_gart_bind(), writing GART PTEs without a TLB flush. This is a local GPU driver ioctl path, not a network protocol.\nAC:L - An attacker with render-node access can reliably trigger GART PTE writes by allocating and binding GTT-domain buffers via standard ioctls; they control mapping timing and concurrency. Uninitialized VRAM contents at driver init are not an attacker-uncontrollable gate for triggering the stale-TLB condition.\nPR:L - All AMDGPU GEM/CS ioctls require DRM_AUTH|DRM_RENDER_ALLOW, which is satisfied by membership in the render/video group on typical desktop, workstation, and cloud-GPU instances\u2014not real root in the init namespace.\nUI:N - Exploitation requires only programmatic ioctl and GPU command submission; no victim interaction such as opening files or mounting filesystems is needed beyond the attacker already having render-node access.\nS:C - Stale garbage GART PTEs in the GPU TLB can cause the GPU to DMA to/from arbitrary physical pages outside the driver\u0027s intended mappings, bypassing the GART/IOMMU address-translation boundary that is supposed to confine GPU memory access.\nC:H - Speculatively loaded garbage PTEs that appear valid can redirect GPU reads to unintended physical memory, including kernel and other processes\u0027 pages, constituting arbitrary memory disclosure via rogue DMA.\nI:H - Those same stale valid PTEs can redirect GPU writes to arbitrary physical addresses, enabling arbitrary memory corruption and potential code execution through DMA write primitives.\nA:H - GPU DMA through invalid or garbage PTEs to unintended physical addresses can cause IOMMU faults, machine checks, GPU hangs, or kernel oops/panic, producing full system availability loss."
            }
          ]
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-08-05T12:35:18.594Z",
        "orgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "shortName": "Linux"
      },
      "references": [
        {
          "url": "https://git.kernel.org/stable/c/40df11255d71b02e20e70579f1b12b687e396e26"
        },
        {
          "url": "https://git.kernel.org/stable/c/91fbb5e635c8fb1b49e15c19da06480089ef719f"
        },
        {
          "url": "https://git.kernel.org/stable/c/8ae8b9e74bab94aab1d79f1688129bcc61c8b29a"
        },
        {
          "url": "https://git.kernel.org/stable/c/b17175d0a375b3ed5e81597dac4983fdb46e478d"
        },
        {
          "url": "https://git.kernel.org/stable/c/791941be5da125d9a1b228582bfdc300c05d05b3"
        },
        {
          "url": "https://git.kernel.org/stable/c/e6c2e6c2e1fa066968a16aca1cb66cd1bdde7741"
        }
      ],
      "title": "drm/amdgpu: zero-initialize GART table on allocation",
      "x_generator": {
        "engine": "bippy-1.2.0"
      }
    }
  },
  "cveMetadata": {
    "assignerOrgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
    "assignerShortName": "Linux",
    "cveId": "CVE-2026-53374",
    "datePublished": "2026-07-19T10:01:58.292Z",
    "dateReserved": "2026-06-09T07:44:35.401Z",
    "dateUpdated": "2026-08-05T12:35:18.594Z",
    "state": "PUBLISHED"
  },
  "dataType": "CVE_RECORD",
  "dataVersion": "5.2"
}


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