CVE-2024-42279 (GCVE-0-2024-42279)
Vulnerability from cvelistv5
Published
2024-08-17 09:08
Modified
2026-05-11 20:29
Severity ?
Summary
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Impacted products
Vendor Product Version
Linux Linux Version: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd
Version: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd
Version: 9ac8d17694b66d54b13e9718b25c14ca36dbebbd
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Show details on NVD website


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              "content": {
                "id": "CVE-2024-42279",
                "options": [
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                    "Exploitation": "none"
                  },
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                    "Automatable": "no"
                  },
                  {
                    "Technical Impact": "partial"
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                "role": "CISA Coordinator",
                "timestamp": "2024-09-10T16:11:42.802690Z",
                "version": "2.0.3"
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        "providerMetadata": {
          "dateUpdated": "2024-09-12T17:33:31.191Z",
          "orgId": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
          "shortName": "CISA-ADP"
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        "title": "CISA ADP Vulnrichment"
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          "product": "Linux",
          "programFiles": [
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          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
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      "cpeApplicability": [
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      "descriptions": [
        {
          "lang": "en",
          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nspi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer\n\nWhile transmitting with rx_len == 0, the RX FIFO is not going to be\nemptied in the interrupt handler. A subsequent transfer could then\nread crap from the previous transfer out of the RX FIFO into the\nstart RX buffer. The core provides a register that will empty the RX and\nTX FIFOs, so do that before each transfer."
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-05-11T20:29:16.986Z",
        "orgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "shortName": "Linux"
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          "url": "https://git.kernel.org/stable/c/3feda3677e8bbe833c3a62a4091377a08f015b80"
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          "url": "https://git.kernel.org/stable/c/45e03d35229b680b79dfea1103a1f2f07d0b5d75"
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        {
          "url": "https://git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927"
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      "title": "spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer",
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    "cveId": "CVE-2024-42279",
    "datePublished": "2024-08-17T09:08:46.829Z",
    "dateReserved": "2024-07-30T07:40:12.261Z",
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    "state": "PUBLISHED"
  },
  "dataType": "CVE_RECORD",
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}


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